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» A Top-Down Microsystems Design Methodology and Associated Ch...
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DATE
2003
IEEE
86views Hardware» more  DATE 2003»
13 years 10 months ago
A Top-Down Microsystems Design Methodology and Associated Challenges
An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodo...
Michael S. McCorquodale, Fadi H. Gebara, Keith L. ...
DATE
2003
IEEE
75views Hardware» more  DATE 2003»
13 years 10 months ago
Circuit and Platform Design Challenges in Technologies beyond 90nm
There are already a huge number of problems for silicon designers and it is likely to just get worse. Many of these problems are technical associated with shrinking geometries and...
Bill Grundmann, Rajesh Galivanche, Sandip Kundu
DAC
1999
ACM
14 years 5 months ago
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology
A 550MHz 64b PowerPC processor was developed for fabrication in Silicon-On-Insulator (SOI) technology from a processor previously designed and fabricated in bulk CMOS [1]. Both th...
D. Allen, D. Behrends, B. Stanisic
DAC
2002
ACM
14 years 5 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
CVPR
2007
IEEE
14 years 7 months ago
Improving Variance Estimation in Biometric Systems
Measuring system performance seems conceptually straightforward. However, the interpretation of the results and predicting future performance remain as exceptional challenges in s...
Ross J. Micheals, Terrance E. Boult