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» A Transactional Architecture for Simulation
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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
13 years 11 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
ICECCS
2010
IEEE
188views Hardware» more  ICECCS 2010»
13 years 5 months ago
A Transactional Architecture for Simulation
Abstract—We are developing a concurrent, agent-based approach to complex systems simulation as part of the CoSMoS project. In such simulations an agent’s behaviour can typicall...
Tim Hoverd, Adam T. Sampson
DAC
2006
ACM
13 years 10 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
DAC
2004
ACM
13 years 10 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
13 years 8 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm