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» A VHDL-based bus model for multi-PCB system design
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FAC
2008
97views more  FAC 2008»
13 years 4 months ago
A functional formalization of on chip communications
This paper presents a formal model and a systematic approach to the validation of communication tures at a high level of abstraction. This model is described mathematically by a fu...
Julien Schmaltz, Dominique Borrione
LCN
2007
IEEE
13 years 11 months ago
Node Connectivity in Vehicular Ad Hoc Networks with Structured Mobility
1 Vehicular Ad hoc NETworks (VANETs) is a subclass of Mobile Ad hoc NETworks (MANETs). However, automotive ad hoc networks will behave in fundamentally different ways than the pred...
Ivan Wang Hei Ho, Kin K. Leung, John W. Polak, Rah...
ICCAD
2006
IEEE
99views Hardware» more  ICCAD 2006»
14 years 1 months ago
Information theoretic approach to address delay and reliability in long on-chip interconnects
With shrinking feature size and growing integration density in the Deep Sub-Micron technologies, the global buses are fast becoming the “weakest-links” in VLSI design. They ha...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
ENTCS
2007
114views more  ENTCS 2007»
13 years 4 months ago
Parametric Performance Contracts for Software Components with Concurrent Behaviour
Performance prediction methods for component-based software systems aim at supporting design decisions of software architects during early development stages. With the increased a...
Jens Happe, Heiko Koziolek, Ralf Reussner
EMSOFT
2007
Springer
13 years 10 months ago
Loosely time-triggered architectures based on communication-by-sampling
We address the problem of mapping a set of processes which communicate synchronously on a distributed platform. The Time Triggered Architecture (TTA) proposed by Kopetz for the co...
Albert Benveniste, Paul Caspi, Marco Di Natale, Cl...