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» A VHDL-based bus model for multi-PCB system design
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EURODAC
1994
IEEE
138views VHDL» more  EURODAC 1994»
11 years 9 months ago
A VHDL-based bus model for multi-PCB system design
In the development of bus-based systems and individual PCB boards interfacing to a bus, the simulation usually requires a specific test bench or creation of quite complex stimuli....
Jari Toivanen, Jari Honkola, Jari Nurmi, Jyrki Tuo...
SIES
2010
IEEE
11 years 3 months ago
Verification of a CAN bus model in SystemC with functional coverage
Abstract--Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which...
Christoph Kuznik, Gilles B. Defo, Wolfgang Mü...
DATE
2006
IEEE
102views Hardware» more  DATE 2006»
11 years 11 months ago
A systematic IP and bus subsystem modeling for platform-based system design
The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of ...
Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-...
HIPEAC
2005
Springer
11 years 11 months ago
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Ke Ning, David R. Kaeli
ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
11 years 10 months ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay
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