4 search results - page 1 / 1 » A VLSI Implementation of a Cascade Viterbi Decoder with Trac... |
ISCAS
1993
IEEE
13 years 8 months ago
1993
IEEE
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
FCCM
2002
IEEE
13 years 9 months ago
2002
IEEE
Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units. W...