12 search results - page 3 / 3 » A Verilog RTL Synthesis Tool for Heterogeneous FPGAs |
SASP
2009
IEEE
14 years 23 days ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip...