70 search results - page 13 / 14 » A Virtual Memory Model for Parallel Supercomputers |
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a comprehensive statistical analysis of workloads collected on data-intensive clusters and Grids. The analysis is conducted at different levels, including Virt...
CCGRID
2001
IEEE
13 years 9 months ago
2001
IEEE
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of high performance of VIA, the previous MPI implementati...
HPCA
2001
IEEE
14 years 5 months ago
2001
IEEE
fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the per...
PPL
2002
13 years 5 months ago
2002
Virtual Interface Architecture(VIA) is a light-weight protocol for protected user-level zero-copy communication. In spite of the promised high performance of VIA, previous MPI imp...
ICS
2004
Tsinghua U.
13 years 10 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...