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ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
13 years 9 months ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
PACS
2000
Springer
99views Hardware» more  PACS 2000»
13 years 8 months ago
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
Power dissipation is a major concern not only for portable systems, but also for high-performance systems. In the past, energy consumption and processor heating was reduced mainly...
Roberto Maro, Yu Bai, R. Iris Bahar
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
13 years 9 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ICASSP
2011
IEEE
12 years 8 months ago
Least squares approximation and polyphase decomposition for pipelining recursive filters
Current techniques used in pipelining recursive filters require significant hardware complexity. These techniques attempt to preserve the exact frequency response of the origina...
Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag