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HOTI
2002
IEEE
13 years 9 months ago
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output...
François Abel, Cyriel Minkenberg, Ronald P....
FSKD
2010
Springer
241views Fuzzy Logic» more  FSKD 2010»
13 years 4 months ago
FUZPAG: A fuzzy-controlled packet aggregation scheme for wireless mesh networks
Abstract--Wireless mesh networks (WMNs) are wireless multihop backhaul networks in which mesh routers relay traffic on behalf of clients or other routers. Due to large MAC layer ov...
Peter Dely, Andreas Kassler, Nico Bayer, Hans Joac...
INFOCOM
1992
IEEE
13 years 8 months ago
Design of Virtual Channel Queue in an ATM Broadband Terminal Adaptor
In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect diffe...
H. Jonathan Chao, Donald E. Smith
HOTI
2005
IEEE
13 years 10 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
INFOCOM
2002
IEEE
13 years 9 months ago
Fair Scheduling and Buffer Management in Internet Routers
Abstract—Input buffered switch architecture has become attractive for implementing high performance routers and expanding use of the Internet sees an increasing need for quality ...
Nan Ni, Laxmi N. Bhuyan