32 search results - page 1 / 7 » A bus architecture for crosstalk elimination in high perform... |
CODES
2006
IEEE
13 years 10 months ago
2006
IEEE
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
VLSID
2005
IEEE
14 years 4 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
ISCA
2012
IEEE
11 years 7 months ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...