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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
10 years 10 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
CASES
2010
ACM
9 years 11 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
PLDI
2005
ACM
10 years 6 months ago
Code placement for improving dynamic branch prediction accuracy
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
Daniel A. Jiménez
CLUSTER
2001
IEEE
10 years 5 months ago
Parallel Standard Cell Placement on a Cluster of Workstations
In this paper we report experiences on a parallel implementation of a standard cell placement algorithm on a cluster of myrinet connected PCs. The proposed algorithm is based on a...
Faris H. Khundakjie, Patrick H. Madden, Nael B. Ab...
ISHPC
2003
Springer
10 years 6 months ago
Code and Data Transformations for Improving Shared Cache Performance on SMT Processors
Simultaneous multithreaded processors use shared on-chip caches, which yield better cost-performance ratios. Sharing a cache between simultaneously executing threads causes excessi...
Dimitrios S. Nikolopoulos
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