121 search results - page 1 / 25 » A cell-based power estimation in CMOS combinational circuits |
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
DAC
1996
ACM
13 years 8 months ago
1996
ACM
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
TVLSI
2002
13 years 4 months ago
2002
The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this brie...
DATE
1998
IEEE
13 years 8 months ago
1998
IEEE
We present an integer-linear-programming-based approach for estimating the maximum instantaneous current through the power supply lines for CMOS circuits. It produces the exact so...