172 search results - page 1 / 35 » A classification of design steps and their verification |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
VLSID
2008
IEEE
14 years 4 months ago
2008
IEEE
This paper demonstrates a formal verificationplanning process and presents associated verification strategy that we believe is an essential (yet often neglected) step in an ASIC o...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
CHI
2006
ACM
14 years 4 months ago
2006
ACM
Studies show that 14-to-40 year olds are spending more time at the computer and less time exercising. Using Contextual Design, our group tackled the challenge of motivating people...