6 search results - page 1 / 2 » A combinatorial group testing method for FPGA fault location |
ACST
2006
13 years 5 months ago
2006
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...
JCO
2008
13 years 4 months ago
2008
The identification of interaction faults in component-based systems has focussed on indicating the presence of faults, rather than their location and magnitude. While this is a va...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
CSREAESA
2008
13 years 6 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...