10 search results - page 2 / 2 » A combined analytical and simulation-based model for perform... |
CGO
2007
IEEE
13 years 8 months ago
2007
IEEE
Dynamic predication has been proposed to reduce the branch misprediction penalty due to hard-to-predict branch instructions. A recently proposed dynamic predication architecture, ...
ISCA
2006
IEEE
13 years 4 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
FCCM
2003
IEEE
13 years 9 months ago
2003
IEEE
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
LCTRTS
2004
Springer
13 years 9 months ago
2004
Springer
Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
JUCS
2000
13 years 4 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...