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FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
13 years 11 months ago
A comparison of via-programmable gate array logic cell circuits
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H...
IAJIT
2010
84views more  IAJIT 2010»
13 years 3 months ago
A Test Procedure for Boundary Scan Circuitry in PLDs and FPGAs
: A test procedure for testing mainly the boundary scan cells, and testing partially the test access port controller in programmable logic devices, and field programmable gate arra...
Bashar Al-Khalifa
MJ
2006
144views more  MJ 2006»
13 years 4 months ago
Design metal-dot based QCA circuits using SPICE model
This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulat...
Rui Tang, Fengming Zhang, Yong-Bin Kim
CDES
2008
90views Hardware» more  CDES 2008»
13 years 6 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
EUROGP
2000
Springer
116views Optimization» more  EUROGP 2000»
13 years 8 months ago
An Extrinsic Function-Level Evolvable Hardware Approach
1 The function level evolvable hardware approach to synthesize the combinational multiple-valued and binary logic functions is proposed in rst time. The new representation of logic...
Tatiana Kalganova