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ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
13 years 11 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
ARITH
2007
IEEE
14 years 3 days ago
Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
Neil Burgess, Chris N. Hinds
LCN
2005
IEEE
13 years 11 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
ASPDAC
2007
ACM
100views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
- For modern processor designs in nanometer technologies, both block and interconnect pipelining are needed to achieve multi-gigahertz clock frequency, but previous approaches cons...
Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong,...
EGH
2004
Springer
13 years 9 months ago
Understanding the efficiency of GPU algorithms for matrix-matrix multiplication
Utilizing graphics hardware for general purpose numerical computations has become a topic of considerable interest. The implementation of streaming algorithms, typified by highly ...
Kayvon Fatahalian, Jeremy Sugerman, Pat Hanrahan