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» A decoupled KILO-instruction processor
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APCSAC
2007
IEEE
13 years 11 months ago
Implicit Transactional Memory in Kilo-Instruction Multiprocessors
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...
Marco Galluzzi, Enrique Vallejo, Adrián Cri...
EUROMICRO
1998
IEEE
13 years 9 months ago
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...
Joan-Manuel Parcerisa, Antonio González
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
11 years 7 months ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
TVLSI
2002
121views more  TVLSI 2002»
13 years 4 months ago
On-chip decoupling capacitor optimization using architectural level prediction
Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills
HICSS
1994
IEEE
106views Biometrics» more  HICSS 1994»
13 years 9 months ago
Trace-Driven Simulation of Decoupled Architectures
The development of accurate trace-driven simulation models has become a key activity in the design of new high-performance computer systems. Tracedriven simulation is fast) enabli...
Sathiamoorthy Manoharan, Nigel P. Topham, A. W. R....