Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix L. While there are...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
Abstract—A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-ar...
Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie...
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...