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TVLSI
2002
144views more  TVLSI 2002»
13 years 4 months ago
On-chip inductance cons and pros
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...
Yehea I. Ismail
ICCAD
2006
IEEE
133views Hardware» more  ICCAD 2006»
14 years 1 months ago
Stable and compact inductance modeling of 3-D interconnect structures
Recent successful techniques for the efficient simulation of largescale interconnect models rely on the sparsification of the inverse of the inductance matrix L. While there are...
Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Ko...
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
14 years 1 months ago
On-chip interconnect modeling by wire duplication
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 1 months ago
INDUCTWISE: inductance-wise interconnect simulator and extractor
Abstract—A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-ar...
Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, Charlie...
VLSID
2000
IEEE
102views VLSI» more  VLSID 2000»
13 years 9 months ago
Inductance Characterization of Small Interconnects Using Test-Signal Method
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal