15 search results - page 2 / 3 » A fault-tolerant directory-based cache coherence protocol fo... |
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
DSD
2009
IEEE
13 years 8 months ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
ICPP
1991
IEEE
13 years 8 months ago
1991
IEEE
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...
CDES
2008
13 years 6 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...