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ICASSP
2011
IEEE
12 years 8 months ago
A flexible high-throughput hardware architecture for a gaussian noise generator
In this paper a exible, high-throughput, low-complexity additive white gaussian noise (AWGN) channel generator is presented. The proposed generator employs a Mersenne-Twister to g...
Ioannis Paraskevakos, Vassilis Paliouras
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
13 years 8 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...
ARC
2008
Springer
175views Hardware» more  ARC 2008»
13 years 7 months ago
Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA
Abstract. Financial applications are one of many fields where a multivariate Gaussian random number generator plays a key role in performing computationally extensive simulations. ...
Chalermpol Saiprasert, Christos-Savvas Bouganis, G...
ICIP
2006
IEEE
14 years 6 months ago
FPGA Architecture for Real-Time Video Noise Estimation
This paper proposes a hardware architecture of a video noise estimation algorithm capable of real-time processing. The objectives consist of adapting a computationally demanding n...
Francois-Xavier Lapalme, Aishy Amer, Chunyan Wang