105 search results - page 1 / 21 » A gate resizing technique for high reduction in power consum... |
ISLPED
1997
ACM
13 years 8 months ago
1997
ACM
With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post
DAC
1999
ACM
14 years 5 months ago
1999
ACM
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
VLSID
2008
IEEE
14 years 4 months ago
2008
IEEE
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
FPL
2010
Springer
13 years 2 months ago
2010
Springer
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...