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DAC
2004
ACM
14 years 4 months ago
A general decomposition strategy for verifying register renaming
This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize re...
Hazem I. Shehata, Mark Aagaard
GLVLSI
2002
IEEE
95views VLSI» more  GLVLSI 2002»
13 years 8 months ago
Term ordering problem on MDG
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
Yi Feng, Eduard Cerny
LCTRTS
2009
Springer
13 years 10 months ago
Live-range unsplitting for faster optimal coalescing
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...
Sandrine Blazy, Benoît Robillard