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EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
9 years 5 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
IOLTS
2007
IEEE
110views Hardware» more  IOLTS 2007»
9 years 7 months ago
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding
In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient i...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
ICPADS
2006
IEEE
9 years 7 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
9 years 5 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
MICRO
1996
IEEE
173views Hardware» more  MICRO 1996»
9 years 5 months ago
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results
The Java bytecode language is emerging as a software distribution standard. With major vendors committed to porting the Java run-time environment to their platforms, programs in J...
Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei ...
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