10 search results - page 2 / 2 » A hybrid self-testing methodology of processor cores |
SAC
2008
ACM
13 years 4 months ago
2008
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
ERSA
2004
13 years 6 months ago
2004
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
IPPS
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we present a methodology for profiling parallel applications executing on the IBM PowerXCell 8i (commonly referred to as the “Cell” processor). Specifically, we...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...