45 search results - page 1 / 9 » A low-SER efficient core processor architecture for future t... |
DATE
2007
IEEE
13 years 10 months ago
2007
IEEE
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
ISCA
2012
IEEE
11 years 6 months ago
2012
IEEE
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
We present an innovative protocol processor component that combines wire-speed processing for low-level, and best effort processing for higher-level protocols. The component is a ...