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ICASSP
2011
IEEE
8 years 11 months ago
A low-power implantable neuroprocessor on nano-FPGA for Brain Machine interface applications
This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interfa...
Fei Zhang, Mehdi Aghagolzadeh, Karim G. Oweiss
ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
10 years 2 months ago
Low-Power Circuits for Brain-Machine Interfaces
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...
Rahul Sarpeshkar, Woradorn Wattanapanitch, Benjami...
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