7 search results - page 1 / 2 » A machine-checked soundness proof for an efficient verificat... |
SAC
2010
ACM
13 years 2 months ago
2010
ACM
Verification conditions (VCs) are logical formulae whose validity implies the correctness of a program with respect to a specification. The technique of checking software properti...
TPHOL
1994
IEEE
13 years 8 months ago
1994
IEEE
Verification Condition Generator (VCG) tools have been effective in simplifying the task of proving programs correct. However, in the past these VCG tools have in general not thems...
ESOP
2006
Springer
13 years 8 months ago
2006
Springer
This paper presents a new program logic designed for facilitating automated reasoning about pointer programs. The program logic is directly inspired by previous work by O'Hea...
CADE
2010
Springer
13 years 5 months ago
2010
Springer
Craig interpolation has become a versatile tool in formal verification, for instance to generate intermediate assertions for safety analysis of programs. Interpolants are typically...
EUROPKI
2009
Springer
13 years 2 months ago
2009
Springer
Efficient zero-knowledge proofs of knowledge (ZK-PoK) are basic building blocks of many cryptographic applications such as identification schemes, group signatures, and secure mult...