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ISPD
2010
ACM
249views Hardware» more  ISPD 2010»
13 years 10 months ago
A matching based decomposer for double patterning lithography
Double Patterning Lithography (DPL) is one of the few hopeful candidate solutions for the lithography for CMOS process beyond 45nm. DPL assigns the patterns less than a certain di...
Yue Xu, Chris Chu
TCAD
2010
194views more  TCAD 2010»
12 years 10 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
ASPDAC
2010
ACM
637views Hardware» more  ASPDAC 2010»
13 years 1 months ago
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography
As Double Patterning Lithography(DPL) becomes the leading candidate for sub-30nm lithography process, we need a fast and lithography friendly decomposition framework. In this pape...
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, D...
ICCAD
2008
IEEE
177views Hardware» more  ICCAD 2008»
14 years 16 days ago
Double patterning technology friendly detailed routing
— Double patterning technology (DPT) is a most likely lithography solution for 32/22nm technology nodes as of 2008 due to the delay of Extreme Ultra Violet lithography. However, ...
Minsik Cho, Yongchan Ban, David Z. Pan
ICCAD
2008
IEEE
141views Hardware» more  ICCAD 2008»
14 years 16 days ago
Layout decomposition for double patterning lithography
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...