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DAC
1996
ACM
13 years 9 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
IEEECIT
2006
IEEE
13 years 11 months ago
The Partitioning Methodology in Hardware/Software Co-Design Using Extreme Programming: Evaluation through the Lego Robot Project
This paper argues about the partitioning in hardware/software co-design and suggests the methodology applying extreme programming to complement the co-design. This approach, contr...
Heeseo Chae, Dong-hyun Lee, Jiyong Park, Hoh Peter...
DATE
2007
IEEE
102views Hardware» more  DATE 2007»
13 years 11 months ago
Efficient testbench code synthesis for a hardware emulator system
: - The rising complexity of modern embedded systems is causing a significant increase in the verification effort required by hardware designers and software developers, leading to...
Ioannis Mavroidis, Ioannis Papaefstathiou
DATE
2003
IEEE
119views Hardware» more  DATE 2003»
13 years 10 months ago
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device
We are investigating an integrated design method for a device driver and a device in order to efficiently develop device drivers used in embedded systems. This paper evaluates wh...
Shinya Honda, Hiroaki Takada
CHARME
2005
Springer
133views Hardware» more  CHARME 2005»
13 years 10 months ago
Symbolic Partial Order Reduction for Rule Based Transition Systems
Partial order (PO) reduction methods are widely employed to combat state explosion during model-checking. In this paper, we develop a partial order reduction algorithm for rule-bas...
Ritwik Bhattacharya, Steven M. German, Ganesh Gopa...