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» A methodology for generating verified combinatorial circuits
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EMSOFT
2004
Springer
13 years 8 months ago
A methodology for generating verified combinatorial circuits
High-level programming languages offer significant expressivity but provide little or no guarantees about resource use. Resourcebounded languages -- such as hardware-description l...
Oleg Kiselyov, Kedar N. Swadi, Walid Taha
TCAD
2002
145views more  TCAD 2002»
13 years 3 months ago
Automatic generation of synthetic sequential benchmark circuits
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
AEI
2008
108views more  AEI 2008»
13 years 4 months ago
Combinatorial synthesis approach employing graph networks
The paper proposes a methodology to assist the designer at the initial stages of the design synthesis process by enabling him/her to employ knowledge and algorithms existing in gr...
Offer Shai, Noel Titus, Karthik Ramani
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
13 years 9 months ago
N-scroll chaotic attractors from a general jerk circuit
— This paper proposes a novel nonlinear modulating function approach for generating n−scroll chaotic attractors based on a general jerk circuit. The systematic nonlinear modula...
Simin Yu, Jinhu Lu, Henry Leung, Guanrong Chen
GLVLSI
2007
IEEE
171views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Combinational equivalence checking for threshold logic circuits
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevo...