160 search results - page 1 / 32 » A methodology for timing model characterization for statisti... |
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
DAC
2006
ACM
13 years 8 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
GLVLSI
2008
IEEE
13 years 10 months ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...