3 search results - page 1 / 1 » A metric for layout-friendly microarchitecture optimization ... |
DAC
2012
ACM
11 years 7 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
ISPD
2012
ACM
12 years 3 days ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...