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DATE
2009
IEEE
101views Hardware» more  DATE 2009»
13 years 10 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl...
ICPP
2008
IEEE
13 years 10 months ago
Mapping Algorithms for Multiprocessor Tasks on Multi-Core Clusters
In this paper, we explore the use of hierarchically structured multiprocessor tasks (M-tasks) for programming multi-core cluster systems. These systems often have hierarchically s...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
12 years 6 months ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross
ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
13 years 10 months ago
ECMon: exposing cache events for monitoring
The advent of multicores has introduced new challenges for programmers to provide increased performance and software reliability. There has been significant interest in technique...
Vijay Nagarajan, Rajiv Gupta
LCTRTS
2009
Springer
13 years 10 months ago
Push-assisted migration of real-time tasks in multi-core processors
Multicores are becoming ubiquitous, not only in general-purpose but also embedded computing. This trend is a reflexion of contemporary embedded applications posing steadily incre...
Abhik Sarkar, Frank Mueller, Harini Ramaprasad, Si...