13 search results - page 1 / 3 » A multicycle communication architecture and synthesis flow f... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
ISPD
2003
ACM
13 years 9 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
For multi-gigahertz synchronous designs in nanometer technologies, multiple clock cycles are needed to cross the global interconnects, thus making it necessary to have pipelined g...
DAC
2003
ACM
14 years 5 months ago
2003
ACM