8 search results - page 1 / 2 » A new look at hardware maze routing |
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper describes a new design for a hardware accelerator to support grid-based Maze Routing. Based on the direct mapped approach of Breuer and Shamsa [3], this work refines th...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Because of the increasing dominance of interconnect issues in advanced IC technology, placement has become a critical step in the IC design flow. To get accurate interconnect inf...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
- In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhan...
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
Interconnect delay dominates system delay in modern circuits, and with reduced feature sizes, coupling capacitance and signal crosstalk have become significant issues. By spacing...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Because of the increasing dominance of interconnect issues in advanced IC technology, it is desirable to incorporate global routing into early design stages to get accurate interco...