252 search results - page 2 / 51 » A novel high throughput reconfigurable FPGA architecture |
FCCM
2009
IEEE
13 years 8 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
ASAP
2006
IEEE
13 years 8 months ago
2006
IEEE
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...