287 search results - page 2 / 58 » A novel improvement technique for high-level test synthesis |
TVLSI
2008
13 years 4 months ago
2008
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
EVOW
2001
Springer
13 years 8 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
DAC
1989
ACM
13 years 8 months ago
1989
ACM
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
ISQED
2007
IEEE
13 years 10 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...