47 search results - page 1 / 10 » A performance counter architecture for computing accurate CP... |
ASPLOS
2006
ACM
13 years 10 months ago
2006
ACM
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
CAL
2006
13 years 4 months ago
2006
Abstract-- Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the e...
SBACPAD
2006
IEEE
13 years 10 months ago
2006
IEEE
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
ICS
2010
Tsinghua U.
13 years 3 months ago
2010
Tsinghua U.
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
ISHPC
1999
Springer
13 years 8 months ago
1999
Springer
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...