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» A performance evaluator for parameterized ASIC architectures
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INFOCOM
2006
IEEE
13 years 11 months ago
Optimal Scheduling Algorithms for Input-Queued Switches
— The input-queued switch architecture is widely used in Internet routers, due to its ability to run at very high line speeds. A central problem in designing an input-queued swit...
Devavrat Shah, Damon Wischik
CIKM
1999
Springer
13 years 9 months ago
Rule-Based Query Optimization, Revisited
We present the architecture and a performance assessment of an extensible query optimizer written in Venus. Venus is a general-purpose active-database rule language embedded in C+...
Lane Warshaw, Daniel P. Miranker
ICDCS
2012
IEEE
11 years 7 months ago
G-COPSS: A Content Centric Communication Infrastructure for Gaming Applications
—With users increasingly focused on an online world, an emerging challenge for the network infrastructure is the need to support Massively Multiplayer Online Role Playing Games (...
Jiachen Chen, Mayutan Arumaithurai, Xiaoming Fu, K...
IPPS
1999
IEEE
13 years 9 months ago
The Impact of Memory Hierarchies on Cluster Computing
Using off-the-shelf commodity workstations and PCs to build a cluster for parallel computing has become a common practice. A choice of a cost-effective cluster computing platform ...
Xing Du, Xiaodong Zhang
CN
2002
117views more  CN 2002»
13 years 5 months ago
Achieving differentiated services through multi-class probabilistic priority scheduling
Differentiated Services (DiffServ) is a promising architecture for the next generation Internet due to its scalable and flexible design. In DiffServ, scheduling disciplines play an...
Chen-Khong Tham, Qi Yao, Yuming Jiang