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» A power and temperature aware DRAM architecture
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DAC
2008
ACM
9 years 4 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem...
HPCA
2006
IEEE
9 years 3 months ago
Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
Ravi K. Venkatesan, Stephen Herr, Eric Rotenberg
APCSAC
2007
IEEE
8 years 7 months ago
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters
Many years of CMOS technology scaling have resulted in increased power densities and higher core temperatures. Power and temperature concerns are now considered to be a primary cha...
Daniel C. Vanderster, Amirali Baniasadi, Nikitas J...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
8 years 9 months ago
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal...
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
9 years 3 months ago
Temperature and Process Variations Aware Power Gating of Functional Units
Technology scaling has resulted in an exponential increase in the leakage power as well as the variations in leakage power of fabricated chips. Functional units (FUs), like Intege...
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sar...
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