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» A power and temperature aware DRAM architecture
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ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
13 years 10 months ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
BSN
2006
IEEE
13 years 8 months ago
eWatch: A Wearable Sensor and Notification Platform
The eWatch is a wearable sensing, notification, and computing platform built into a wrist watch form factor making it highly available, instantly viewable, ideally located for sen...
Uwe Maurer, Anthony Rowe, Asim Smailagic, Daniel P...
DAC
2009
ACM
14 years 5 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...