44 search results - page 2 / 9 » A reuse scenario for the VHDL-based hardware design flow |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
ASPDAC
2012
ACM
12 years 1 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
DASIP
2010
13 years 8 days ago
2010
Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
AHS
2007
IEEE
13 years 9 months ago
2007
IEEE
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...