34 search results - page 2 / 7 » A sample-based cache mapping scheme |
ICCD
2007
IEEE
13 years 9 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
ICS
1997
Tsinghua U.
13 years 9 months ago
1997
Tsinghua U.
This paper makes the case for the use of XOR-based placement functions for cache memories. It shows that these XOR-mapping schemes can eliminate many conflict misses for direct-ma...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Fetching instructions from a set-associative cache in an embedded processor can consume a large amount of energy due to the tag checks performed. Recent proposals to address this ...
RT
2001
Springer
13 years 9 months ago
2001
Springer
: The performance of hardware-based interactive rendering systems is often constrained by polygon fill rates and texture map capacity, rather than polygon count alone. We present a...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
This paper presents a method of using texture mapping with mipmapping to render a VLSI layout. Texture mapping is used to save already rasterized areas of the layout from frame to...