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GLOBECOM
2008
IEEE
13 years 11 months ago
Evaluating the Performance on ID/Loc Mapping
—Challenges of routing scalability has attracted many research efforts, represented by the works of splitting identifier and locator semantics of IP addresses. A group of identi...
Hong Zhang, Maoke Chen, Yuncheng Zhu
SAS
2007
Springer
108views Formal Methods» more  SAS 2007»
13 years 11 months ago
Programming Language Design and Analysis Motivated by Hardware Evolution
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...
Alan Mycroft
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
13 years 9 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens