15 search results - page 1 / 3 » A simple, verified validator for software pipelining |
POPL
2010
ACM
14 years 1 months ago
2010
ACM
Software pipelining is a loop optimization that overlaps the execution of several iterations of a loop to expose more instruction-level parallelism. It can result in first-class p...
WADT
2001
Springer
13 years 8 months ago
2001
Springer
Abstract. We consider the verification of a simple pipelined microprocessor in Maude, by implementing an equational theoretical model of systems. Maude is an equationally-based la...
VMCAI
2005
Springer
13 years 9 months ago
2005
Springer
Interval computations, stochastic arithmetic, automatic differentiation, etc.: much work is currently done to estimate and to improve the numerical accuracy of programs but few c...
MICRO
2005
IEEE
13 years 10 months ago
2005
IEEE
Until recently, a steadily rising clock rate and other uniprocessor microarchitectural improvements could be relied upon to consistently deliver increasing performance for a wide ...
ENTCS
2002
13 years 4 months ago
2002
The paper presents approaches to the validation of optimizing compilers. The emphasis is on aggressive and architecture-targeted optimizations which try to obtain the highest perf...