8 search results - page 1 / 2 » A system-on-a-chip lock cache with task preemption support |
CASES
2001
ACM
13 years 8 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
ECRTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
RTAS
2008
IEEE
13 years 11 months ago
2008
IEEE
Real-time schedulability theory requires a priori knowledge of the worst-case execution time (WCET) of every task in the system. Fundamental to the calculation of WCET is a schedu...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose in this paper an algorithm for off-line selection of the contents of on-chip memories. The algorithm supports two types of on-chip memories, namely locked caches and sc...
LCTRTS
2000
Springer
13 years 8 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...