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» A theory of Error-Rate Testing
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ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 1 months ago
A theory of Error-Rate Testing
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
Shideh Shahidi, Sandeep Gupta
DATE
2008
IEEE
104views Hardware» more  DATE 2008»
13 years 10 months ago
Multi-Vector Tests: A Path to Perfect Error-Rate Testing
The importance of testing approaches that exploit error tolerance to improve yield has previously been established. Error rate, defined as the percentage of vectors for which the...
Shideh Shahidi, Sandeep Gupta
PAMI
1998
87views more  PAMI 1998»
13 years 4 months ago
What Size Test Set Gives Good Error Rate Estimates?
—We address the problem of determining what size test set guarantees statistically significant results in a character recognition task, as a function of the expected error rate. ...
Isabelle Guyon, John Makhoul, Richard M. Schwartz,...
IOLTS
2007
IEEE
120views Hardware» more  IOLTS 2007»
13 years 10 months ago
Accelerating Soft Error Rate Testing Through Pattern Selection
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
FPGA
2005
ACM
105views FPGA» more  FPGA 2005»
13 years 9 months ago
Soft error rate estimation and mitigation for SRAM-based FPGAs
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
Ghazanfar Asadi, Mehdi Baradaran Tahoori