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ASPDAC
2012
ACM
247views Hardware» more  ASPDAC 2012»
12 years 1 months ago
Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
— In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
Xin Zhao, Sung Kyu Lim
ASPDAC
2012
ACM
265views Hardware» more  ASPDAC 2012»
12 years 1 months ago
GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Di...
Duo Ding, Bei Yu, David Z. Pan
ASPDAC
2012
ACM
279views Hardware» more  ASPDAC 2012»
12 years 1 months ago
Block-level 3D IC design with through-silicon-via planning
— Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 1 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
ASPDAC
2012
ACM
238views Hardware» more  ASPDAC 2012»
12 years 1 months ago
Design for manufacturability and reliability for TSV-based 3D ICs
—The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technolog...
David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Mo...