36 search results - page 1 / 8 » Accelerating Architectural Simulation by Parallel Execution ... |
HICSS
1994
IEEE
14 years 2 months ago
1994
IEEE
MASCOTS
2007
14 years 5 days ago
2007
—Modern micro-architecture simulators are many orders of magnitude slower than the hardware they simulate. The use of multiprocessor architectures for supporting future mobile an...
IPPS
1999
IEEE
14 years 3 months ago
1999
IEEE
VLIW machines possibly provide the most direct way to exploit instruction level parallelism; however, they cannot be used to emulate current general-purpose instruction set archit...
RTAS
2008
IEEE
14 years 5 months ago
2008
IEEE
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
EUROPAR
2009
Springer
14 years 5 months ago
2009
Springer
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...